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Asymmetric Multiprocessing

Asymmetric Multiprocessing unites two different cores in one chip.
The advantage of this architecture is the strict separation of real-time relevant tasks -e.g. control algorithm- from rest of the system. Normally both cores can access all peripheries. An exception is the NXP i.MX 7ULP which has e.g. an own UART periphery for each core.

peripherals


F&S Elektronik Systeme uses NXP processors which unite an ARM Cortex-A core and an additional ARM Cortex-M core on one chip.
So the customer can use a high-performance operating system like Linux or Windows Embedded (Compact/10 IoT) on the Cortex-A and simulateously a C++ program or the real-time operating system FreeRTOS on the Cortex-M. This allows completely new application fields. For example, the Cortex-M can fulfill hard real-time requirements. Interfaces like CAN and I²C can be operated within miliseconds by the F&S native bootloader and the Cortex-M. It is also easy to switch off the Cortex-A and let the Cortex-M process background tasks to reduce the power consumption.

usecases

Both cores are attached to an internal interconnect-bus-matrix and have access to the complete periphery (exception: i.MX 7ULP). Along with ARM® modules for memory protection (SCU and TrustZone), NXP has integrated a Resource Domain Controller (RDC). This makes it easy to isolate both cores from each other. All available interfaces and memory areas can easily be assigned to one core or both.

For the core communication the semaphore unit SEMA with minimum 16 hardware semaphores and a messaging unit (MU) are available. Messages between the cores can be sent easily with the messaging unit. Every core has minimum four send and receive mailboxes.

MessagingUnit

➜  F&S Elektronik Systeme also offers a workshop on asymmetric multiprocessing